1. Field of the Invention
The present invention relates to a parallel databus and to a method for the communication of two assemblies by means of such a databus. The invention particularly refers to a parallel databus, which is suitable for a multiprocessor architecture. Given such a multiprocessor architecture, a plurality of processor systems basically having equal rights can communicate with one another via the databus.
2. Description of the Related Art
The multibus II (multibus is a registered trademark of the Intel Corporation) represents such a databus. The multibus II is a synchronized bus defined in IEEE Standard for a High-Performance Synchronous 32-bit bus: MULTIBUS II, The Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, NY 10017, USA, 1988. In order to make it more simple, the “MULTIBUS II” is referred to as “multibus” in the following.
The hardware realization of such a multibus consists of a backplane, in which the signal lines of the bus are arranged and which are provided with approximately 20 cable connectors, whereby an assembly can be respectively connected thereto. FIG. 3 schematically shows two assemblies 2 that are connected via a multibus 1. Each assembly 2 has a databus driver 3 that is immediately connected to the signal lines of the multibus 1 and has a controller 4 that is connected to the databus driver 3. The controller 4, in turn, is connected to the electronic physical units of the assembly 2. These electronic physical units can have a processor or merely represent a passive digital circuit.
The controller 4, corresponding to the protocol of the multibus 1, logically edits the data generated by the electronic physical units and forwards them to the databus driver 3. The databus driver 3 converts the data into electrical data signals that are appropriate for the multibus and applies the electrical data signals to the signal lines. Data signals coming from the multibus 1, in a reversed way, are accepted by the databus driver, which forwards the data to the controller 4. The controller 4 correspondingly edits the data for the processing by the electronic physical units.
The databus drivers are transparent electronic physical units, i.e., the respective corresponding input side and output side of the databus driver assumes the same logical value. Since the databus drivers are transparently fashioned, an active connection between two assemblies 2 is logically through-switched from the controller 4 of the one assembly 2 to the controller 4 of the other assembly 2.
The signal propagation time between the two controllers 4 limits the maximum transmission frequency or, respectively, bus frequency. Corresponding to the aforementioned IEEE standard, the bus frequency is 10 MHz. A transmission rate of 40 byte/s is obtained by such a bus frequency.
A study “20 MHZ MULTIBUS II PARALLEL SYSTEM BUS INVESTIGATION, TAUFIK MA, INTEL CORPORATION, 8 APRIL, 1991” planned to operate the multibus with a bus frequency of 20 MHz. For this purpose, extensive adaptations and modifications have been proposed in order to optimize the individual runtimes between the controllers and databus drivers or, respectively, between the databus drivers connected via the multibus. The aim of this study is to operate a multibus having 10 assemblies at a maximum and 20 MHz, and to operate a multibus having 20 assemblies at a maximum and 16 MHz. The signal propagation time between the controllers of two assemblies would have to be reduced to 50 ns or less. The result of this study is that such an “accelerated” multibus is theoretically possible, however, there would be a considerable developing outlay until its actual realization. Younger data busses, such as the PCI bus, do not have bus drivers in order to obtain faster access to the signal lines of the databus and therefore obtain a higher throughput. These data busses, however, are limited with respect to the number of assemblies to be connected at a maximum, which is normally clearly smaller than 10, and its physical expanse is limited to 10 cm, for example. On the other hand, a multibus can be up to 50 cm long and can connect 20 assemblies to one another, whereby a plurality of assemblies can represent processor systems of equal rights.
The publication by “Färber, G., Bussysteme, R. Oldenbourg Verlag, Munich 1987 (2. edition)” describes functions and structures of bus systems on the pages 16–19. On page 19, image 13 shows a handshake transmission. The article “Packer, Stephen et. al., Message Passing Supports Multiple Processor Design, Computer Design” of 15 Jun. 1984, pages 117–120, 122 and 124 describes measures for improving the communication in the multibus II.